An Efficient Online BIST Architecture for NoCs
نویسندگان
چکیده
This paper presents an offline/online concurrent scan based built-in-self-test (scan-BIST) method for a Network-onChip (NoC) based SoC. The proposed architecture contains a special scan cell and an Embedded Test Core (ETC) as its test source. The ETC performs a static flow control and a centric average power consumption control during the proposed test mechanism. To reduce the test vector traffic, the ETC uses a multicasting approach to send a test vector to multiple cores, simultaneously. Inserting only one clock cycle stall in the normal operation of a core, the proposed cell architecture applies a test vector to the core-under-test and captures its output response.
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